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EVENTS
7 Apr 11 TSMC U.S. Tech ...
Austin, Texas
25 Oct 11 2011 ARM Tech ..
Santa Clara, California
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IC Chip Engineering Inc offers state of art design services in chip
level ASICs. Our
flexible business model allows you to choose onsite,
offsite, or offshore consulting.
We have expertise in Logic Design &
Verification, Design for Testability (DFT),
Physical Design &
Verification
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ICCE offers a wide range of "idea to chip" services with
both on and off site
engagement models. The team is comprised of
experienced engineering professionals
with areas of expertise across the
entire design flow. ICCE has a proven track record
in taking complex
ASIC designs from design specification through tape-out, so whether
you're looking for architectural guidance or in need of additional resources for
logic
design, physical implementation, and/or verification, ICCE's
team can help at any
stage in your design flow.
ICCE has successfully implemented full-chip and block level customer
tape-outs in
40nm, 65nm, and 90nm technology nodes. Over a dozen joint SoC
development
projects have been completed in market segments including
portable devices, consumer
electronics, and wired and wireless
networking.
ICCE has and continues to implement first time working silicon.
Our team focuses
on addressing the unique requirements of your design
including ultra low power
operation, stringent die size requirements, high
speed interface design, or complex
analog and mixed signal IP integration.
We aim to exceed your expectations.
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RTL/Verification
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Architecture
definition/partition and RTL coding in Verilog/VHDL
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Verification
using the latest tools such as Vera
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IP
integration and verification using industry standard bus interfaces
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Verification
and integration of IP such as PCI Express(PCIE), and USB
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Formal
verification using Conformal and SV assertion based verification
Synthesis/DFT
and Timing closure
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Timing
closure using Primetime and industry standard synthesis tools
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Primetime
static
timing analysis to avoid any violations after the synthesis
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Scripting
using TCL language and creating a synthesis environment
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Floorplan
based synthesis to reduce the close the timing much
faster
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Offer
smooth migration to industry standard physical design tools
Design
for Testability
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Scan
insertion using full, parallel, and partial scan methodology
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BIST
controller for testing the embedded memory blocks
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JTAG
controller for debugging the boundaries and for debugging the software
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ATPG
vectors generation for testing the manufacturing defects
Physical
Design and Verification
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Physical
synthesis, place, route, congestion reduction and Floor planning
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DRC
and LVS to check integrity of the design
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Clock
skew management, insertion and signal integrity issues
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Timing
closure and post-layout simulation and formal verification
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Verifying
40nm physical design issues, DFM, antenna and reliability VIAS fixes
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20+
corner block level timing closure and ECO runs for hold and setup
violations
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Tools:
Magma, Synopsys, Primetime, Conformal and IC Compiler
In
order to be successful with an on-site engineering contracts the main
thing we
need to understand is what are the exact job requirements and
responsibilities for the
on site contract engineers?
We know this sounds
basic, but based on many engagements on-site this is one problem
that
slows the process down at critical design stages. We help facilitate
precise contract
requirements including priority of particular skills and
percentage of job skills that will be
used on a project by offering to
consult with client hiring managers at no cost.
We then actually write the
contract job requirements ourselves that then get approved
by the client
hiring mangers. We also offer options the hiring mangers may not realize
are available to them. For example in some cases we can do a contract to a
permanent
position within the client company assuming everyone involved
wants to move in that
direction.
We can provide 1 up a small team of 10
people to help with your hardware design projects.
As a review, our focus
is for providing contract resources in the fields of our hardware
expertise.
One of the big fears of doing a Turnkey Project is “How
Do We Support The Design Once Completed?” Rest assured we have
dealt successfully with this issue very effectively in the past.
Below are
just a few examples of how to deal with this for both large and small
clients
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Our 10 person ASIC
engineering team not only completed two USB ASIC designs but also
trained 20 mid-level engineers from large Fortune 10 Semiconductor
Company in ASIC Design.
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Once our team was completed the newly trained
team completed documentation, finished production engineering
modifications and did on-going support of the designs after we
completed.
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We put
engineers “On Call” to be available on short notice to help with
any post hand off issues as part of the package.
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