ICC Compiler Floorplan
Floorplanning describes a process of laying the foundation for physical
implementation. As the capabilities of conventional floorplan tools increase
such as virtual prototyping, mixed mode(macro & standard cell) placement,
and quick-placement based pin optimization in the past few years,
floorplan tasks have expanded into many different areas.
Furthermore, top level versus block level tasks can be quite different. Block level
floorplan tasks include macro placement, pin placement/optimization, IO buffering,
and power planning whereas top level floorplan tasks include logical/physical
hierarchy planning, block partitioning, place/route based block pin optimization,
and feed through insertion/placement.
At ICCE, utilizing the automated and proprietary ICCE flow, physical design
experts can achieve optimal floorplan in both block level and top level by exploring
different options and possibilities that today's floorplanning tools offer.
ICC Compiler Placement
Placement of today's complex SoC designs can be a challenging task as there are
many different placement optimization constraints such as timing, area, power,
SI, DFM, and more.
At ICCE, we ensure the best quality of placement through analyzing and applying
the right set of constraints for each design by understanding the most important
objective of the design. As the industry standard placement tools are equipped with
various physical synthesis/optimization capabilities/options, ICCE's placement experts
can achieve the best quality of result by applying the following optimization
techniques with the right set of options.
Attenuation buffer insertion/placement
Shielding buffer insertion/placement
High fanout net synthesis
Design constraint fixing
Multi-Vt gate swapping
Setup/hold time fixes
Congestion cost optimization
ICC Compiler Clock Tree Synthesis (CTS)
CTS is an essential task in ASIC design as both performance and functionality
of an integrated circuit depend on the characteristics of the clock network.
Typically, the goal of CTS is to minimize the global clock skew
amongst the sequential elements in a design, otherwise known as zero skew
Today's ASIC designers face a set of challenges that are far greater than just
minimizing global clock skew due to emerging technologies such as integrated
clock gating cells, multi-Vt/multi-Vdd methodologies, and useful clock skew
methodology. Several deep sub micron effects suh as on-chip variation, IR-drop, and
temperature inversion effect can also influence CTS strategies.
Furthermore, chip-level CTS can present a set of different challenges than
block level CTS, such as dealing with clock latencies in blocks/macros,
understanding the clock structure properly to put "synch"(clock leaf)
points, and dealing with inter-clock skews among synchronous clocks and
ICCE has successfully implemented ASIC designs with clock networks that
range from a handful to over 50 and a frequency range of 80MHz to 866MHz in
130nm, 90nm, and sub-90nm technology nodes.
Our CTS experts, equipped with the CTS flow, can manage complex CTS issues
such as gated clocks, inter-clock skew control, clock tree level control, minimizing local
skew with integrated clock gating (ICG) cells, and minimizing global skew with ease.
Because of sub-90nm effects such as SI, crosstalk, and DFM issues,
the routing phase
has become one of the most key stages in timing/power/DFM closure in ASIC designs.
In 65nm/90nm technologies, routing tools can utilize a number of routing layers
ranging between 8 to 12 layers. While the degree of freedom that
comes from the ability to utilize many routing layers(up to 12 or more) is helpful
for routing, properly managing these resources can be quite challenging.
At ICCE, our expert design team tackles tough routing issues through a set of
routing strategies that include crosstalk driven routing, critical net/group 2Cuting,
shielded routing, and area-based routing.In addition, several post-route optimization
methodologies have been developed by ICCE's routing flow to ensure