IC Chip Engineering Inc  

                An ASIC implementation solutions company

 

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18 Jan 11 Comm  Platform ...
Santa Clara, California
5 Apr 11 TSMC U.S. Tech ...
San Jose, California
7 Apr 11 TSMC U.S. Tech ...
Austin, Texas
31 May 11 TSMC U.S. Tech ...
Shanghai, China
18 Oct 11 TSMC OIP ECO ..
San Jose, California
25 Oct 11 2011 ARM Tech ..
Santa Clara, California

 

 

 

 

 

Our strategy is to meet the needs of our clients who need a critical IC module 
done turnkey  due to critical time factors or they don’t want to spend extra
money on expensive EDA tools like Cadence or Synopsys.  Other times they
need one or up to a small team of Elite  On-Site Contract Engineering or 
EDA resources for “Peak Load” situations or to meet a deadline. 
 
Still other times they need to build a permanent team to sustain long term 
design projects.  In addition to the design services and training business units 
in place. We are  expanding into IP product development as well. 
 
We are currently working on IP modules for new markets and selling other
Intellectual Property  IP. Lastly, as part of our expansion efforts we are in
process of negotiating with several new and established EDA vendors to 
offer both sales and support for key strategic EDA products  to our clients.
 
Designers need access to a wide variety of IP blocks of differing size and
complexity, from the basic arithmetic blocks to  memory controllers, 
signal processing, and protocol interfaces. 
 
ICCE and its third-party IP partners offer a broad portfolio of off-the-shelf, 
configurable IP cores optimized cores. Licensed and unlicensed IP is delivered 
and can be requested directly from the website.

 

We offer reusable soft IP for high speed applications. All our IPs are 
coded in verilog HDL. These IPs go through rigorous verification 
before getting released to you. The verification is done using VERA

 

If the customer is a stealth mode startup or migrating into a ASIC from an 
RTL based on an FPGA  we an implement a baseline EDA vendor recommended 
flow for a target foundry for a large SOC with block level as well as fullchip 
flow down to 22nm processes.

 

Combining our soft-IP or customer provided soft IP we can harden the IP with 
our state of the art methodology, the integration of customer required foundry 
libraries for synthesis,  DFT and Physical Design through gds2 for  processes down
to 22nm.

 

 

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Last modified: October 25, 2011